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K7D323674A K7D321874A
1Mx36 & 2Mx18 SRAM
32Mb A-die DDR SRAM Specification
153FCBGA with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev 1.4 Oct. 2005
K7D323674A K7D321874A
Document Title
32M DDR SYNCHRONOUS SRAM
1Mx36 & 2Mx18 SRAM
Revision History
Rev No. Rev. 0.0 Rev. 0.1 History Initial document. Remove /G operation thru the Spec. - Remove /G from PUNCTIONAL BLOCK DIAGRAM, PIN CONFIGURATION, TRUTH TABLE and TIMING WAVEFORMs Add 300MHz Speed bin. - Add Part ID at ORDERING INFORMATION & IDD30 at DC CHARACTERISTICS Change ILI and ILo at DC CHARCATERISTICS - ILI : MIN -1 -> -3, MAX 1 -> 3, ILo : MIN -1 -> -5, MAX 1 -> 5 Change the comment of Programmable Impedance Output Driver. Change RECOMMENDED DC OPERATING CONDITIONS. - VREF : Min 0.68 -> 0.65, Max 1.0 -> 0.85 Change PIN CAPACITANCE : CIN : 3 -> 3.1 Change AC TEST CONDITIONS : TR/RF: 0.4/0.4 -> 0.5/0.5 Change AC TIMING CHARACTERISTICS - tCHCL : tKHKL -0.1 -> tKHKL -0.2 , tCLCH : tKLKH -0.1 -> tKLKH -0.2 - tCXCV : 2.10 -> 2.30 Rev 0.2 Change VDDQ RANGE - In FEATURES : 1.5V VDDQ -> 1.5~.1.8V VDDQ - In RECOMENDED DC OPERATING CONDITIONS : Max VDDQ : 1.6 -> 1.9 Change TRUTH TABLE : Remove Clock Stop Change DC CHARACTERISTICS - x36 IDD : IDD50 : 950 -> 1050, IDD45 : 850 -> 950, IDD40: 800 -> 860, IDD30: 750 -> 760 - x18 IDD: IDD50 : 850 -> 1000, IDD45 : 800 -> 900, IDD40: 750 -> 810, IDD30: 700 -> 710 - ISB1 : 150 -> 200 Change PIN CAPACITANCE : CIN : 3.1 -> 3.2, COUT : 4 -> 4.2 Change AC TIMING CHARACTERISTICS - MIN tKHKL, tKHKL : -40 : 1.1 -> 1.2, -30 : 1.1 -> 1.4 - MIN tAVKH, tBVKH, tKHAX, tKHBX : -45 : 0.25 -> 0.27 - tKXCV MIN/MAX : 0.8/2.3 -> 1.0/2.5 Change PACKAGE THERMAL CHARACTERISTICS Feb. 2003 Advance Draft Data Dec. 2002 Jan. 2003 Remark Advance Advance
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
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Rev 1.4 Oct. 2005
K7D323674A K7D321874A
Revision History
Rev No. Rev 0.3 History
1Mx36 & 2Mx18 SRAM
Draft Data May. 2003
Remark Advance
Change DC CHARACTERISTICS - x36 IDD : IDD50 : 1050 -> 1150 , IDD45 : 950 -> 1050, IDD40: 860 -> 960, IDD30: 760 -> 860 - x18 IDD: IDD50 : 1000 -> 1100, IDD45 : 900 -> 1000, IDD40: 810 -> 910, IDD30: 710 -> 810 - ISB1 : 200 -> 300 Change 300Mhz speed bin to 333Mhz Change PIN CONFIGURATIONS - change DQ pin number Change AC CHARACTERISTICS - tCHCL, tCLCH : -/+0.2 -> -/+ 0.1
Rev 0.4 Rev 0.5
Jun. 2003 Aug. 2003
Advance Advance
Rev 0.6
Change AC CHARACTERISTICS - Remove : tQTRK, tCXCV - Add : tCXCH,tCXCL,tCHQV,tCLQV,tCHQX,tCLQX,tCLQZ,tCHLZ Add Power-Up/Power-Down Supply Voltage Sequencing Change PACKAGE PIN CONFIGURATIONS - Remove the number at DQ pins Change Bin - 50, 45, 40, 33 -> 40, 37, 33 Change the word in READ OPERATION - at least one NOP -> at least two NOP Add AC INPUT CHARACTERISTICS and AC INPUT DEFINITION. Remove the comment for DDR3 from Spec. Modify AC TIMING CHARACTERISTICS - clock high/low pulse width : -40 : 1.2 -> 1.15 - remove min. value of tCHQV and tCLQV Add Pb free.
Sep. 2003
Advance
Rev 0.7 Rev 0.8
Sep. 2003 Oct. 2003
Advance Advance
Rev 0.9
Feb. 2003
Advance
Rev 1.0
Mar. 2003
Final
Rev 1.1 Rev 1.2 Rev 1.3
Apr. 2004 Jun. 2004 Jan. 2005
Final Final Final
Rev 1.4
Oct. 2005
Final
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Rev 1.4 Oct. 2005
K7D323674A K7D321874A
FEATURES
1Mx36 or 2Mx18 Organizations. 1.8~2.5V VDD/1.5V ~1.8VDDQ. HSTL Input and Outputs. Single Differential HSTL Clock. Synchronous Pipeline Mode of Operation with Self-Timed Late Write. * Free Running Active High and Active Low Echo Clock Output Pin. * Registered Addresses, Burst Control and Data Inputs. * * * * *
1Mx36 & 2Mx18 SRAM
* Registered Outputs. * Double and Single Data Rate Burst Read and Write. * Burst Count Controllable With Max Burst Length of 4 * Interleved and Linear Burst mode support * Bypass Operation Support * Programmable Impedance Output Drivers. * JTAG Boundary Scan (subset of IEEE std. 1149.1) * 153(9x17) Flip Chip Ball Grid Array Package(14mmx22mm) * No Output enable support.
GENERAL DESCRIPTION
The K7D323674A and K7D321874A are 37,748,736 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as 1,048,576 words by 36 bits for K7D323674A and 2,097,152 words by 18 bits for K7D321874A, fabricated using Samsung's advanced CMOS technology. Single differential HSTL level clock, K and K are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of K clock, all addresses and burst control inputs are registered internally. Data inputs are registered one cycle after write addresses are asserted(Late Write), at the rising edge of K clock for single data rate (SDR) write operations and at rising and falling edge of K clock for a double data rate (DDR) write operations. Data outputs are updated from output registers off the rising edges of K clock for SDR read operations and off the rising and falling edges of K clock for DDR read operations. Free running echo clocks are supported which are representative of data output access time for all SDR and DDR operations. The chip is operated with 1.8~2.5V power supply and is compatible with HSTL input and output. The package is 9x17(153) Ball Grid Array balls on a 1.27mm pitch.
ORDERING INFORMATION
Part Number K7D323674A-H(G)C40 K7D323674A-H(G)C37 K7D323674A-H(G)C33 K7D321874A-H(G)C40 K7D321874A-H(G)C37 K7D321874A-H(G)C33
* G : Lead free package
Organization
Maximum Frequency 400MHz
1Mx36
375MHz 333MHz 400MHz
2Mx18
375MHz 333MHz
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Rev 1.4 Oct. 2005
K7D323674A K7D321874A
FUNCTIONAL BLOCK DIAGRAM
SA[0:20]( or SA[0:21]) Address Register CE 20(or 21) 18(or 19) (Burst Address) Burst Counter (Burst Write Address) 20(or 21) 18(or 19) 2:1 MUX
1Mx36 & 2Mx18 SRAM
Dec. Data Out
K,K
Clock Buffer
Memory Array 1Mx36 or (2Mx18)
Data In 36(or18)x2 W/D Array 36(or18)x2 Write Buffer
Comparator B1 B3 Advance Co Control SD/DD Write Address Register (2 stage) CE Synchronous Select & R/W control CE R/W LD Internal Clock Generator Data Output Strobe Data Output Enable State Machine Strobe_out
36(or 18)x2 S/A Array 36(or 18)x2 2 : 1 MUX
B2
Output Buffer
Echo Clock Output
Data In Register (2 stage)
36(or 18) DQ CQ,CQ
XDIN
PIN DESCRIPTION
Pin Name K, K SA SA0, SA1 DQ CQ, CQ B1 B2 B3 LBO ZQ Pin Description Differential Clocks Synchronous Address Input Synchronous Burst Address Input (SA0 = LSB) Synchronous Data I/O Differential Output Echo Clocks Load External Address Burst R/W Enable Single/Double Data Selection Linear Burst Order Output Driver Impedance Control Input Pin Name TCK TMS TDI TDO VREF VDD VDDQ VSS NC Pin Description JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output HSTL Input Reference Voltage Power Supply Output Power Supply GND No Connection
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Rev 1.4 Oct. 2005
K7D323674A K7D321874A
PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7D323674A(1Mx36)
1 A B C D E F G H J K L M N P R T U VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS 2 VDDQ DQ VDDQ DQ VDDQ CQ VDDQ DQ VDDQ DQ VDDQ CQ VDDQ DQ VDDQ DQ VDDQ 3 SA SA SA SA VSS DQ VSS DQ VSS DQ VSS DQ VSS NC* VDD(4) SA TMS 4 SA VSS SA Vss(5) VDD VDD VSS VDD VDD VSS LBO VDD VDD VSS SA VSS TDI 5 ZQ B1 SA VDD VREF VDD K K VDD B2 B3 VDD VREF VDD(2) SA1 SA0 TCK 6 SA VSS SA Vss(6) VDD VDD VSS VDD VDD VSS
1Mx36 & 2Mx18 SRAM
7 SA SA SA SA VSS DQ VSS DQ VSS DQ VSS DQ VSS SA VDD(3) SA NC
8 VDDQ DQ VDDQ DQ VDDQ CQ VDDQ DQ VDDQ DQ VDDQ CQ VDDQ DQ VDDQ DQ VDDQ
9 VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS
MODE(7) VDD VDD VSS SA VSS TDO
K7D321874A(2Mx18)
1 A B C D E F G H J K L M N P R T U VSS NC VSS DQ VSS NC VSS DQ VSS NC VSS DQ VSS NC VSS DQ VSS 2 VDDQ DQ VDDQ NC VDDQ CQ VDDQ NC VDDQ DQ VDDQ NC VDDQ DQ VDDQ NC VDDQ 3 SA SA SA SA VSS NC VSS DQ VSS NC VSS DQ VSS SA VDD(4) SA TMS 4 SA VSS SA Vss(5) VDD VDD VSS VDD VDD VSS LBO VDD VDD VSS SA VSS TDI 5 ZQ B1 SA VDD VREF VDD K K VDD B2 B3 VDD VREF VDD(2) SA1 SA0 TCK 6 SA VSS SA Vss(6) VDD VDD VSS VDD VDD VSS MODE(7) VDD VDD VSS SA VSS TDO 7 SA SA SA SA VSS DQ VSS NC VSS DQ VSS NC VSS SA VDD(3) SA NC 8 VDDQ NC VDDQ DQ VDDQ NC VDDQ DQ VDDQ NC VDDQ CQ VDDQ NC VDDQ DQ VDDQ 9 VSS DQ VSS NC VSS DQ VSS NC VSS DQ VSS NC VSS DQ VSS NC VSS
(1) Variable address see "Variable address assignment table" (2) Variable address see "Variable address assignment table" (3) Variable address see "Variable address assignment table" (4) Variable address see "Variable address assignment table" (5) Variable address see "Variable address assignment table" (6) Variable address see "Variable address assignment table" (7) Internally NC
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Rev 1.4 Oct. 2005
K7D323674A K7D321874A
VARIABLE ADDRESS ASSIGNMENT TABLE
Density 32 Mb 64 Mb 144 Mb 288 Mb 576 Mb 1152 Mb Ball 5C (1) SA SA NC SA NC SA Ball 5P (2) VDD SA SA SA SA SA Ball 7R (3) VDD VDD SA SA SA SA Ball 3R (4) VDD VDD SA SA SA SA
1Mx36 & 2Mx18 SRAM
Ball 4D (5) Vss Vss Vss Vss SA SA
Ball 6D (6) Vss Vss Vss Vss SA SA
NOTE : - SRAM density definition beyond 144Mb will include the parity bits.
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Rev 1.4 Oct. 2005
K7D323674A K7D321874A
Read Operation(Single and Double)
1Mx36 & 2Mx18 SRAM
During SDR read operations, addresses and controls are registered at the first rising edge of K clock and then the internal array is read between first and second rising edges of K clock. Data outputs are updated from output registers off the second rising edge of K clock. During DDR read operations, addresses and controls are registered at the first rising edge of K clock, and then the internal array is read twice between first and second rising edges of K clock. Data outputs are updated from output registers sequentially by burst order off the second rising and falling edge of K clock. Interleave and linear burst operation is controlled by LBO pin and the burst count is controllable with the maximum burst length of 4. To avoid data contention,at least two NOP operations are required between the last read and the first write operation.
Write Operation(Late Write)
During SDR write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered at the following rising edge of K clock. During DDR write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered twice at the following rising and falling edge of K clock. Write addresses and data inputs are stored in the data in registers until the next write operation, and only at the next write opeation are data inputs fully written into SRAM array.
Echo clock operation
Free running type of Echo clocks are generated from K clock regardless of read, write and NOP operations. They will stop operation only when K clock is in the stop mode. Echo clocks are designed to represent data output access time and this allows the echo clocks to be used as reference to capture data outputs outputs.
Bypass Read Operation
Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are identical. For this case, data outputs are from the data in registers instead of SRAM array.
Programmable Impedance Output Driver
The data output and echo clock driver impedance are adjusted by an external resistor, RQ, connected between ZQ pin and VSS, and are equal to RQ/5. For example, 250 resistor will give an output impedance of 50. Output driver impedance tolerance is 15% by test(10% by design) and is periodically readjusted to reflect the changes in supply voltage and temperature. Output driver impedance is updated every 64 clock cycles of Non-Read operation (Write or NOP) but since the echo clock drivers are in operation even during Non-Read operation, the impedance is update only the drivers are not in operation. Therefore impedance updates for "0s" or pull down drivers occur whenever the echo clock driver is driving "1s" or vice versa. Furthermore, to guarantee optimum output driver impedance after power up, the SRAM need 2048 deselect (or write) cycles.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-down.
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Rev 1.4 Oct. 2005
K7D323674A K7D321874A
TRUTH TABLE
K B1 H L L L L H B2 L H H L L H B3 X H L H L X DQ Hi-Z DOUT DOUT DIN DIN B
1Mx36 & 2Mx18 SRAM
Operation No Operation, Pipeline High-Z Load Address, Single Read Load Address, Double Read Load Address, Single Write Load Address, Double Write Increment Address, Continue
NOTE : - B(Both) is DIN in write cycle and DOUT in read cycle. Byte write function is not supported. X means "Don't Care". - K & K are complementary.
OUTPUT TRISTATE TRUTH TABLE
K Operation Write (B2=L) Deslect (NOP) (B1=H, B2=L) DQ (n) X X DQ (n+1) High-Z High-Z
BURST SEQUENCE TABLE
4 Burst Operation for Interleaved Burst (LBO = VDDQ)
Interleaved Burst A1 First Address
Case 1
A0 A1
Case 2
A0 A1
Case 3
A0 A1
Case 4
A0
Fourth Address
0 0 1 1
0 1 0 1
0 0 1 1
1 0 1 0
1 1 0 0
0 1 0 1
1 1 0 0
1 0 1 0
NOTE : - For Interleave Burst LBO = VDDQ is recommended. If LBO = VDD, it must not exceed 2.63V.
4 Burst Operation for Linear Burst (LBO = VSS)
Linear Burst Mode First Address
Case 1
A1 A0 A1
Case 2
A0 A1
Case 3
A0 A1
Case 4
A0
Fourth Address
0 0 1 1
0 1 0 1
0 1 1 0
1 0 1 0
1 1 0 0
0 1 0 1
1 0 0 1
1 0 1 0
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Rev 1.4 Oct. 2005
K7D323674A K7D321874A
BUS CYCLE STATE DIAGRAM
1Mx36 & 2Mx18 SRAM
LOAD NEW ADDRESS
,B B2
3
,B
B1 B2 ,B
3
3
B1
B2
,B B2
B1
B1
3
READ SDR
WRITE SDR
READ DDR
WRITE DDR
B1, B2
B1, B2
B1, B2
B1, B2
B1, B2
B1, B2
B1, B2 B1, B2 B1, B2
INCREMENT ADDRESS B1, B2
INCREMENT ADDRESS B1, B2 B1, B2
INCREMENT ADDRESS
INCREMENT ADDRESS
B1, B2
B1, B2
POWER UP
NO OP
NOTE : 1. State transitions ; B1 =(Load Address), B1=(Increment Address, Continue) B2 =(Read), B2 =(Write) B3 =(Single Data Rate), B3 =(Double Data Rate)
B1, B2
B1, B2
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Rev 1.4 Oct. 2005
K7D323674A K7D321874A
ABSOLUTE MAXIMUM RATINGS
Parameter Core Supply Voltage Relative to VSS Output Supply Voltage Relative to VSS Voltage on any pin Relative to VSS Output Short-Circuit Current(per I/O) Storage Temperature Maxmum Junction Temperature Maxmum Power Dissipation Symbol VDD VDDQ VIN IOUT TSTR TJ PD
1Mx36 & 2Mx18 SRAM
Value -0.5 to 3.13 -0.5 to 2.3 -0.5 to VDDQ+0.5 (2.3V MAX) 25 -55 to 125 110 3.0
Unit V V V mA C C W
NOTE : Power Dissipation Capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data. Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Parameter Core Power Supply Voltage Output Power Supply Voltage Input High Level Voltage Input Low Level Voltage Input Reference Voltage Symbol VDD VDDQ VIH VIL VREF Min 1.7 1.4 VREF+0.1 -0.3 0.68 Typ 2.5 1.5 0.75 Max 2.6 1.9 VDDQ+0.3 VREF-0.1 1.0 Unit V V V V V 1, 2 1, 3 Note
NOTE :1. These are DC test criteria. DC design criteria is VREF50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 2. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=2.6V (2.1V for DQs) (pulse width 20% of cycle time). 3. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.0V (-0.5V for DQs) (pulse width 20% of cycle time).
DC CHARACTERISTICS
Parameter Average Power Supply Operating Current(x36) (Cycle time = tKHKH min) Average Power Supply Operating Current(x18) (Cycle time = tKHKH min) Stop Clock Standby Current (VIN=VDD-0.2V or 0.2V fixed, K=Low, K=High) Input Leakage Current (VIN=VSS or VDDQ) Output Leakage Current (VOUT=VSS or VDDQ) Output High Voltage(Programmable Impedance Mode) Output Low Voltage(Programmable Impedance Mode) Output High Voltage(IOH=-0.1mA) Output Low Voltage(IOL=0.1mA) Symbol IDD40 IDD37 IDD33 IDD40 IDD37 IDD33 ISB1 ILI ILO VOH1 VOL1 VOH2 VOL2 Min Max 960 940 900 910 890 850 300 3 5 VDDQ VDDQ/2 VDDQ 0.2 Unit mA Note 1,2
-
mA
1,2
-3 -5 VDDQ/2 VSS VDDQ-0.2 VSS
mA A A V V V V
1
3 4
NOTE :1. Minimum cycle. IOUT=0mA. 2. 50% read cycles. 3. |IOH|=(VDDQ/2)/(RQ/5)15% @VOH=VDDQ/2 for 175 RQ 300. 4. |IOL|=(VDDQ/2)/(RQ/5)15% @VOL=VDDQ/2 for 175 RQ 300.
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Rev 1.4 Oct. 2005
K7D323674A K7D321874A
PIN CAPACITANCE
Parameter Input Capacitance Data Output Capacitance Symbol CIN COUT Test Condition VIN=0V VOUT=0V
1Mx36 & 2Mx18 SRAM
TYP -
Max 3.2 4.2
Unit pF pF
NOTE : Periodically sampled and not 100% tested.(TA=25C, f=500MHz)
AC INPUT CHARACTERISTICS
Parameter AC Input Logic High AC Input Logic Low Clock Input Differential Voltage VREF Peak-to-Peak AC Voltage Symbol VIH (AC) VIL (AC) VDIF (AC) VREF (AC) 0.8 5% VREF (DC) Min VREF + 0.4 VREF - 0.4 Max Unit V V V V Note -
AC INPUT DEFINITION
CK VDIF(AC) CK
VIH(AC) VREF VIL(AC) Setup Time Hold Time
AC TEST CONDITIONS(TA=0 to 70C, VDD=2.37 -2.63V, VDDQ=1.5V)
Parameter Input High/Low Level Input Reference Level Input Rise/Fall Time Output Timing Reference Level Clock Input Timing Reference Level Output Load Symbol VIH/VIL VREF TR/TF Value 1.25/0.25 0.75 0.5/0.5 0.75 Cross Point See Below Unit V V ns V V Note -
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Rev 1.4 Oct. 2005
K7D323674A K7D321874A
AC TEST OUTPUT LOAD
50 50 25 DQ 0.75V 50 50 5pF 5pF
1Mx36 & 2Mx18 SRAM
0.75V
0.75V
AC TIMING CHARACTERISTICS
PARAMETER Clock Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width Setup Times Address Setup Time Control(B1,B2,B3) Setup Time Data Setup Time Hold Times Address Hold Time Control(B1,B2,B3) Hold Time Data Hold Time Output Times Echo Clock High Pulse Width Echo Clock Low Pulse Width Clock Crossing to Echo Clock Clock Crossing to Echo Clock Echo Clock High to Output Vaild Echo Clock Low to Output Valid Echo Clock High to Output Hold Echo Clock Low to Output Hold Echo Clock High to Output High-Z Echo Clock High to Output Low-Z tCHCL tCLCH tCXCH tCXCL tCHQV tCLQV tCHQX tCLQX tCHQZ tCHLZ -0.20 -0.20 -0.20 0.20 -0.20
tKHKL-0.1 tKLKH-0.1 tKHKL+0.1 tKLKH+0.1 tKHKL-0.1 tKLKH-0.1 tKHKL+0.1 tKLKH+0.1 tKHKL-0.1 tKLKH-0.1 tKHKL+0.1 tKLKH+0.1
SYMBOL
-40 MIN 2.50 1.15 1.15 0.30 0.30 0.20 0.30 0.30 0.20 MAX 5.00 MIN 2.67 1.25 1.25 0.33 0.33 0.25 0.33 0.33 0.25
-37 MAX 6.00 MIN 3.00 1.40 1.40 0.35 0.35 0.30 0.35 0.35 0.30
-33 MAX 6.00
UNITS NOTES
tKHKH tKHKL tKLKH tAVKH tBVKH tDVKX tKHAX tKHBX tKXDX
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1
2
2
2 2
1.0 1.0
2.5 2.5 0.20 0.20
1.0 1.0
2.5 2.5 0.20 0.20
1.0 1.0
2.5 2.5 0.20 0.20
3 3
-0.20 -0.20 0.20
-0.20 -0.20 0.20 -0.20
ns ns
Notes: 1. The maximum cycle time must be limited to guarantee AC timing specification.
2. This parameter is guaranteed by design, and may not be tested at values shown in the table. 3. This parameter refers to CQ and CQ rising and falling edges. 4. This parameter is only for 32Mb density 5. K and K Clocks must be used differencitally to meet AC timing specifications.
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Rev 1.4 Oct. 2005
K7D323674A K7D321874A
1Mx36 & 2Mx18 SRAM
TIMING WAVEFORMS FOR DOUBLE DATA RATE CYCLES (Burst Length=4, 2)
READ READ READ CONTINUE READ CONTINUE READ NOP (burst of 4) (burst of 4) (burst of 2)
NOP
NOP 8
(burst of 4)
WRITE 9
WRITE 10
CONTINUE READ (burst of 4)
READ
CONTINUE
1
2
3
4
5
6
7
11
12
K
tKHKH
K
B1
B2
tBVKH tKHBX
B3
SA
tAVKH
A0 tKHAX
A5
A1
A2
A3
tKHDX tDVKH
DQ
QX2
Q01
Q02
Q03
Q04
Q51
Q52
Q53
Q54
Q11
Q12
D21
D22
D23
D24
Q31
tKXCH tCHQV tCHQZ tCHLZ
tCHQX
tCLQV
tCLQX
tKXCL tCHCL tCLCH
CQ CQ
DON'T CARE UNDEFINED
NOTE 1. Q01 refers to output from address A. Q02 refers to output from the next internal burst address following A, etc. 2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present. 3. Doing more than one Read Continue or Write Continue will cause the address to wrap around.
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Rev 1.4 Oct. 2005
K7D323674A K7D321874A
1Mx36 & 2Mx18 SRAM
TIMING WAVEFORMS FOR SINGLE DATA RATE CYCLES
(Burst Length=4, 2, 1)
READ CONTINUE READ READ CONTINUE CONTINUE
NOP
READ (burst of 4)
READ NOP (burst of 1)
NOP 8
(burst of 2)
WRITE 9
WRITE 10
CONTINUE READ CONTINUE (burst of 2)
READ 12
1
2 tKHKH
3
4
5
6
7
11
K
tKHKL tKLKH
K
B1
B2
tBVKH tKHBX
B3
SA
tAVKH
A0 tKHAX
A1
A2 tDVKH
A3
tKHDX
DQ
QX1
Q01
Q02
Q03
Q04
Q11
D21
D22
Q31
tKXCH tCHQV tCHQZ tCHLZ tCHQX tKXCL tCHCLtCLCH
CQ CQ
DON'T CARE UNDEFINED
NOTE : 1. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0, etc. 2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present. 3. This devices supports cycle lengths of 1, 2, 4. Continue(B1=HIGH, B2=HIGH, B3=X) up to three times following a B1 operation. Any further Continue assertions constitute invalid operations. 4. This device will have an address wraparound if further Continues are applied.
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Rev 1.4 Oct. 2005
K7D323674A K7D321874A
1Mx36 & 2Mx18 SRAM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and therefore can be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0 Instruction 0 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 EXTEST IDCODE PRIVATE3 SAMPLE PRIVATE2 PRIVATE1 BYPASS TDO Output Boundary Scan Register Identification Register Bypass Register Boundary Scan Register Bypass Register Bypass Register Bypass Register
Notes
1 2 1 3,5 4 3,5 3,5 3
SAMPLE-Z Boundary Scan Register
SRAM CORE SA SA
1 1 1
TDI
BYPASS Reg. Identification Reg. Instruction Reg. Control Signals
TDO
TMS TCK
TAP Controller
NOTE : 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. Input terminators are switched off. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. Bypass register is initiated to VSS when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 4. SAMPLE instruction dose not places DQs in Hi-Z. 5. PRIVATE1 and PRIVATE2 are reserved for the exclusive use of SAMSUNG. This instruction should not be used.
TAP Controller State Diagram
1 0 Test Logic Reset
0
Run Test Idle
1
Select DR
1
Select IR 0 1 Capture IR 0 Shift IR 1
1
1
0 1
Capture DR
0
Shift DR
0
0
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
0 0
Pause IR 1 Exit2 IR 1 Update IR 1
0 0 0
1
Exit2 DR
1
1
Update DR
0
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Rev 1.4 Oct. 2005
K7D323674A K7D321874A
BOUNDARY SCAN EXIT ORDER(x36)
1
1Mx36 & 2Mx18 SRAM
BOUNDARY SCAN EXIT ORDER(x18)
SA SA SA VSS(2 SA SA SA SA DQ19 DQ20 DQ28 DQ18 DQ30 CQ(3) DQ21 DQ27 DQ29 DQ31 ZQ(1) B1 B2 B3 LBO DQ22 DQ24 DQ26 DQ32 CQ(3) DQ23 DQ35 DQ25 DQ33 DQ34 VDD(2) SA SA
NC
5P 5R 5T 6R 7T 7R 7P 8T 9T 8P 7M 9P 8M 9M 7K 8K 9K 6L 5H 5G 9H 8H 7H 9F 8F 9D 7F 8D 9B 8B 7D 7C 7B 7A 6D 6C 6A
VDD(2) SA1 SA0 SA SA VDD(2) SA DQ1 DQ2 DQ10 DQ0 DQ12 CQ(3) DQ3 DQ9 DQ11 DQ13 MODE K K DQ4 DQ6 DQ8 DQ14 CQ(3) DQ5 DQ17 DQ7 DQ15 DQ16 SA SA SA SA VSS(2) SA SA
38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73
74
5C 4A 4C 4D 3A 3B 3C 3D 2B 1B 2D 3F 1D 2F 1F 3H 2H 1H 5A 5B 5K 5L 4L 1K 2K 3K 1M 2M 1P 3M 2P 1T 2T 3R 3T 4R
7U
1 2 3 4 5 6 7 8
5P 5R 5T 6R 7T 7R 7P 8T
VDD(2) SA1 SA0 SA SA VDD(2) SA DQ1
28 29 30 31 32 33 34 35 36
5C 4A 4C 4D 3A 3B 3C 3D 2B
SA SA SA VSS(2) SA SA SA SA DQ10
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
9 10 11 12 13 14 15 16 17
9P 8M 7K 9K 6L 5H 5G 8H 9F
DQ2 CQ(3) DQ0 39 DQ3 MODE K K DQ6 DQ4 46 2K 1M DQ15 DQ13 40 41 42 43 44 45 1H 5A 5B 5K 5L 4L DQ12 ZQ(1) B1 B2 B3 LBO 3H DQ9 37 38 1D 2F DQ11 CQ(3)
18 19 20 21 22 23 24 25 26 27
7F 8D 9B 7D 7C 7B 7A 6D 6C 6A
DQ8 DQ7 DQ5
47
48 SA SA SA SA VSS(2) SA SA 49 50 51 52 53 54 55
3M 2P 1T 3P 3R 3T 4R 7U
DQ17 DQ16 DQ14 SA VDD(2) SA SA NC
* Reserved for Mode Pin
* Reserved for Mode Pin
NOTE : 1. If pin is connected as they should, TDO will be low. If pin is open, TDO will be high 2. This pin is place holder for higher density. TDO will be low for VSS and high for VDD 3. CQ and CQ are outputs during boundary scan. CQ reflects the input to K and CQ outputs the inverted value of K. It is prohibited to force CQ and CQ. And TDO is 'X'.(Don't Care)
SCAN REGISTER DEFINITION
Part 1M x 36 2M x 18 Instruction Register 3 bits 3 bits Bypass Register 1 bits 1 bits ID Register 32 bits 32 bits Boundary Scan 74 bits 55 bits
- 17
Rev 1.4 Oct. 2005
K7D323674A K7D321874A
ID REGISTER DEFINITION
Part 1M x 36 2M x 18 Revision Number (31:28) 0000 0000 Part Configuration (27:18) 01000 00100 01001 00011 Vendor Definition (17:12) XXXXXX XXXXXX
1Mx36 & 2Mx18 SRAM
Samsung JEDEC Code (11: 1) 00001001110 00001001110
Start Bit (0) 1 1
JTAG DC OPERATING CONDITIONS
Parameter Power Supply Voltage Input High Level Input Low Level Output High Voltage(IOH=-2mA) Output Low Voltage(IOL=2mA) Symbol VDD VIH VIL VOH VOL Min 1.7 0.65*VDD -0.3 0.75*VDD VSS Typ 2.5 Max 2.6 VDD+0.3 0.35*VDD VDD 0.25*VDD Unit V V V V V Note
NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter Input High/Low Level Input Rise/Fall Time Input and Output Timing Reference Level
NOTE : 1. See SRAM AC test output load on page 5.
Symbol VIH/VIL TR/TF
Min VDD/0.0 1.0/1.0 VDD/2
Unit V ns V
Note
1
JTAG AC Characteristics
Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Input Setup Time TMS Input Hold Time TDI Input Setup Time TDI Input Hold Time Clock Low to Output Valid Symbol tCHCH tCHCL tCLCH tMVCH tCHMX tDVCH tCHDX tCLQV Min 50 20 20 5 5 5 5 0 Max 10 Unit ns ns ns ns ns ns ns ns Note
JTAG TIMING DIAGRAM
TCK
tCHCH tCHCL tMVCH tCHMX tCLCH
TMS
tDVCH
tCHDX
TDI
tCLQV
TDO
- 18
Rev 1.4 Oct. 2005
K7D323674A K7D321874A
PACKAGE DIMENSIONS
153-FCBGA-14.00x22.00 LID
METAL LID UNDERFILL
1Mx36 & 2Mx18 SRAM
Units:millimeters/Inches
0.300 MAX M
#A1
7.000
(Datum A)
14.000 1.27x8=10.160 5.080 987654321
A #A1 INDEX B A BCDE FGH J K LMNPR T U
11.000
(Datum B) 1.27x16=20.320
20.000 22.000
10.160
0.750 MIN
0.750 MIN
12.000 14.000 TOP VIEW
0.150 MAX
1.270 BSC
1.270 BSC
153-0.7600.150
BOTTOM VIEW 0.200 0.600 UNDERFILL 2.750
153 BGA PACKAGE THERMAL CHARACTERISTICS
Parameter Junction to Case Junction to Board Junction to Ambient(at air flow of 1m/sec) Junction to Ambient(at still air) Symbol JC JB JA JA Thermal Resistance 0.9 6.9 16.1 19.5 Unit C/W C/W C/W C/W Note
NOTE : 1. Junction temperature can be calculated by : TJ = TA + PD x JA or TJ = TC + PD x JC 2. Strongly recommends using a heat sink because it greatly improves the ambient temperature requirement
1.200
22.000
- 19
Rev 1.4 Oct. 2005

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